Seeking Senior ASIC/SoC Physical Design Engineer in Mountain View, CA. Join our AI hardware startup with $150K - $300K salary, equity, and innovative projects. Design high-performance silicon from RTL to GDS for AI applications. Collaborate with team...
Seeking a forward-thinking technologist with expertise in Digital Implementation and Signoff to drive innovation at Synopsys. Develop technology roadmap, collaborate with teams, and champion cutting-edge solutions. MS/PhD with 15+ years experience in...
Seeking GIS Analyst with 3 years' experience using ESRI suite in an Enterprise setting. Duties include data analysis, creating 3D models, automating workflows, and providing technical support. Requires a related degree, proficiency in ArcGIS Pro, and...
Seeking a Senior SoC Timing Engineer with expertise in full chip STA runs, timing closure, and optimizing design constraints for cutting-edge AI, ML Processor Chips at a Startup. Responsibilities include developing STA flows, eco timing methodology, ...
Join us at Synopsys, a pioneer in cutting-edge Silicon IP technology transforming AI, autonomous vehicles, and more. Seeking a Senior CAD Engineering Manager to spearhead advanced methodologies, tools, and technology for ASIC design. Showcase your ex...
Join Aeva's innovative team as a Silicon Technical Program Manager for cutting-edge 4D LiDAR development. Lead ASIC physical implementation, collaborate with cross-functional teams, and ensure high-quality deliverables. Competitive salary, equity, an...
Seeking a Staff Logic Design Engineer to join Synopsys' dynamic team. Develop innovative firmware for cutting-edge FPGA-based emulation systems. Ideal candidates have a background in Electrical/Computer Engineering, expertise in Verilog, and hands-on...
Seeking a seasoned Sr. SoC Physical Design Engineer for high-level SoC Integration. Exciting role at a dynamic startup focusing on cutting-edge ASICs for AI, ML Processor Chips. Responsibilities include full chip planning, top-level integration, timi...
Join Synopsys, the driving force behind cutting-edge technologies like self-driving cars and AI. We seek a Physical Design Specialist to elevate chip design projects and optimize performance. Required: Place & Route, Clock Tree Synthesis, Advanced Ti...
Seeking skilled Senior DFT Engineer in Mountain View, CA for MBIST Logic Insertion, Scan Logic Insertion, pattern generation, and validation. Must have 8+ years’ experience with DFT concepts, Verilog, RTL coding, and clock synchronization. Competitiv...
