Sr. ASIC/SoC Physical Design Engineer
Location
Mountain View, CA | United States
Job description
Job Title: Sr. ASIC/SoC Physical Design Engineer
Job Location: Mountain View, CA - hybrid on-site 3 days/week
Compensation: $150K - $300K+ Depending on experience plus generous equity!
Requirements: Physical Design, ASIC/SoC Design, RTL to GDS, Floorplanning, Timing Closure, Routing
Our company is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. We are seeking silicon physical design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for our products across compute, memory management. High-speed connectivity and other key technologies.
Top Reasons to Work with Us
1) Competitive Compensation ($150K - $300K+ Depending on Experience)
2) Comprehensive Benefits package including equity!
3) The chance to work for a small disruptive company in the AI hardware space!
What You Will Be Doing
- Contribute to our silicon design and physical design methodology with a scalable solution across blocks, subsystems, full-chip designs from RTL to GDS
- Own entire subsystem or subsets and/or chip-level physical design deliverables including but not limited to: floor-planning, placement, clock insertion, routing, optimizations, timing closure analysis, physical verification closure, electrical analysis, etc.
- Plan and drive intermediate and sign-off reviews as well as execution progress reporting based on key PPA metrics-tracking towards various silicon milestones including design freeze and tapeout
- Work closely with the design, DFT and other physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results
- Work with design services partners and other critical third-party vendors and partners on planning and executing block-level and chip-level closure for blocks you own and oversee
What You Need for this Position
Bachelors (Master's or Ph.D. preferred) in Electrical Engineering, or similar with 3+ years of experience in the following:
- RTL-to-silicon experience in driving physical design for subsystems and/or top-level functions with ASICs and SOCs from early RTL design and netlist to production silicon
- Production-proven experience with Floorplanning, place and route, clock tree insertion and analysis, timing analysis, physical verification, electrical sign-off and related areas to produce tapeout ready GDS for large physical blocks and/or top-level
- Project experience in collaborating with design, verification and DFT teams to structure and partition the design optimally for PPA and sign-off
- Experience in working with a third-party design services partner and taking subsystems and/or top-level from initial floor plan to sign-off and tapeout is a plus
So, if you are a Sr. ASIC/SoC RTL Design Engineer with experience, please apply today! or send an updated copy of your resume to [email protected] for immediate consideration!
Benefits - Medical/Dental/Vision
- PTO/Vacation Days
- Equity
Colorado employees will receive paid sick leave. For additional information about available benefits, please contact Mike Vandenbergh
Applicants must be authorized to work in the U.S.
Preferred Skills
Physical Design
ASIC Design
SOC design
Floorplanning
RTL to GDS
Tapeout
Routing
Timing Closure
Job tags
Salary
$150k - $300k
