SR. SOC PHYSICAL DESIGN ENGINEER

Location

Mountain View, CA | United States

Job description

Description

We are looking for a Sr. SoC Physical Design Engineer with experience working on Top Level SoC Integration, IO Ring, Bump assembly, Power delivery, Clock planning, RDL Routing, IP integration as well as experience working on IP subsystems and Hierarchical blocks. This is an exciting opportunity to be part of a fast-paced Startup culture doing world-class ASICs on AI, ML Processor Chips at advanced process technology nodes. 

Responsibilities 

• The candidate must have hands-on experience in full chip SoC top level integration and will be responsible for full chip planning, IO planning, Bump assembly, IO Ring, Top level power grid, Clock design, RDL routing and IP integration.
• The candidate will also be responsible for full chip timing closure, EMIR closure, physical verification, and packaging support. 
• Hands-on experience to run spice on the top-level clock network is preferred.
• The candidate must be able to take blocks from RTL through to clean GDS and collaborate with the design team and other PD engineers driving to signoff closure.
• The candidate should be well versed with low power upf flow working on multi voltage and multi clock domain designs.
• The candidate should be able to debug constraints, do physical aware Synthesis, mmmc based low power optimization, synthesize clock trees meeting stringent skew and insertion delay targets, signal integrity aware routing, delay matching and do PV clean DRC/LVS, Signoff STA and EMIR closure.
• The candidate should be able to run through blocks STA closure and should be able to probe reports, debug and collaborate closely with RTL designers to achieve timing closure and best PPA.
• The candidate must be very good at scripting, probing blocks to derive insightful metrics and aiding in the overall improvement of the PPA metrics.
• Methodologies and automation are key to the success of any PD team. The candidate will drive improvements to our tool flows starting from RTL through to GDS.
• To deliver top quality chips, we must work cross-functionally. The candidate will collaborate effectively with all parts of engineering: Architecture, RTL Design and Verification.
• We are a results-driven team. The candidate should be able to adopt a data-driven approach, assess the TAT for the Top level and the blocks owned, should periodically document the results, assess the progress and PPA improvements.
• The candidate will be mentoring junior engineers or interns and aid in knowledge sharing with a giver mindset.

Qualifications 

• BS/MS in Electrical Engineering or equivalent
• 10+ years ASIC Physical Design experience and 5+ years of SoC Top level integration experience with successful tapeouts at the latest technology nodes (7nm experience preferred) 
• Strong interpersonal and collaboration skills
• Experience with large SOCs that utilize 3rd Party design IP
• Knowledge of advanced and highly automated RTL to GDS flows including timing budgeting, synthesis, place & route, static timing analysis (STA), logic equivalence checking (LEC), EMIR, and LVS/DRC
• Strong engineering mindset, startup mentality, versatility, and interpersonal skills
• Demonstrates good judgment in selecting methods and techniques for obtaining solutions
• Proficiency with EDA tools: FC, DC, ICC2, StarRC, PrimetimeSI, ICV, Redhawk, etc.
• Experience in full product life cycle from 1st Tapeout to metal spins to full silicon production
• Proficiency in using scripting languages like TCL, Perl, etc.
• Experience with UPF and low-power multi-voltage designs

Benefits  

• Base salary range is $100,000 - $300,000
• The actual salary of a successful applicant may vary from the posted range based on a candidate’s experience, training, education, location and/or other legitimate business reasons.
• You will also be eligible for stock options and benefits.

Job tags

Salary