Hiring RTL Design
4-12 years
Location:
Kochi/Trivandrum/Ahmedabad/Bangalore/Vizag
·
Architecture Development
o Experience in developing High Level Architecture for a Design Requirement from Specification level
o Extract Micro Architecture from H...
Hi Folks
Greetings from Tech Mahindra!!
Role: RTL Engineer
Exp: 4+ years
Location: Bangalore/ Kochi/ Ahmedabad/ Vizag
Job Description
Sound knowledge of RTL design and front-end design tools and f...
.../ Working Experience on debugging Tool Flows & Setup related issues is an added advantage
Protocol Knowledge (IPs / Processors / IO Bus Protocols etc., )
Ability to Understand complex SOC architecture concepts th...
...coding of High Definition VESA VDC-M-1.1/1.2 Video Codec products targeted towards AR/VR, MIPI DSI, HDMI 2.1 and DisplayPort Protocols,H.263/H.264 Video codecs, Reed Solomon FEC encoder and Decoder as per IEEE 802.3...
...Roles & Responsibilities: 1. Understand Functional requirements and translate to RTL Design; Design and Implement signal processing algorithms in RTL 2. Verilog programming
3. Design and Implement Control & Interf...
...capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
We are looking for ASIC Front-end Implementat...
Hiring RTL Design
4-12 years
Location:
Kochi/Trivandrum/Ahmedabad/Bangalore/Vizag
·
Architecture Development
o Experience in developing High Level Architecture for a Design Requirement from Specification level
o Extract...
...HMs team for overall timing closure for SoC
Primetime and Tempus knowledge is essential
Leakage recovery, Vmin targets and performance v/s leakage trade-off is essential knowledge for final sign-off
Deep scripting k...
Exciting Opportunity for Senior RTL Design Engineer
Are you a seasoned professional with over 3 years of experience in RTL Design? We're... ...and testing RTL designs, as well as debugging and trou...
1. Proficient in Verilog coding and RTL design, data path designs, 2. Knowledge of RTL checks ex- LINT, SDC, CDC
3. Familiar with synthesis flow and timing constraints
4. Experience in writing Verilog testbench and running simulations.
5. Desir...
