ASIC Digital Design, Staff Engineer

Location

Bangalore | India

Job description

• The candidate will be part of the R&D in Solutions Group at our Bangalore Design Center, India
• The position offers learning and growth opportunities
• This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include IP Design using latest HDL and design Flows

Job Description

The candidate will be part of the Synopsys IP Design R&D team at Synopsys. You will own RTL architecture design, micro architecture design , clock partitioning, RTL realization in System Verilog, Design Flow Clean up, Product documentation and Release As part of the work, you will closely work with and lead and mentor a team of RTL designers and be part of a global team of experienced Engineers.


Technical Expertise needed :

• Must have BSEE in EE with 7+ years of relevant experience or MSEE with 6+ years of relevant experience in the following areas:
• Own RTL Micro architecture Design and RTL coding of High Definition VESA VDC-M-1.1/1.2 Video Codec products targeted towards AR/VR, MIPI DSI, HDMI 2.1 and DisplayPort Protocols,H.263/H.264 Video codecs, Reed Solomon FEC encoder and Decoder as per IEEE 802.3-bj,ck,bs specifications, BCH codes, Streaming FFT engines, Fixed Point Arithmetic
• Knowledge of one or more of protocols/standards: VESA VDC-M, DSC, HDMI 2.1, MIPI DSI, AMBA (AXI,APB,AHB)
• Hands-on experience in translating the algorithm specification given in C/C++ to Micro architecture and RTL Design for area, latency, throughput trade-offs
• Hands-on experience with control path oriented designs like asynchronous FIFOs, SPRAM/ DPRAM interface design, and designs with multiple clocks involving various Clock Domain Crossing schemes.
• Hands on experience with Synthesizable and concise parameterizable System Verilog RTL coding for ASIC designs and Simulation tools
• Hands on experience in writing self checking Verilog Testbenches to verify module level designs
• Experience with Perforce or similar revision control environment
• Hands-on experience in TCL, Python scripting for automation.
• Exposure to quality processes in the context of IP design and verification is an added advantage

Job Responsibilities include -

• Understand Standard Specifications, create Functional Specifications for the product and create architecture and micro-architecture with detailed design documents. Propose and enhance the product with unique and differentiating features beyond what is specified by standard specifications
• Be single point of contact with hands-on experience on all design tasks - Micro Architecture design - propose various options for Area, Timing, perform Logic levels analysis and throughput trade-offs
• Own and drive Lint, CDC,RDC,DFT clean up, Synthesis flows, static timing flows, Formal checking, etc
• Co-own RTL coding of design, Design flows like - synthesis, CDC, RDC analysis, STA, Power estimation
• Perform peer review of RTL code for continuous quality and QoR improvements
• Review of Verification plan, coverage plan, coverage reports and share feedback with verification team for coverage improvement
• Own debug of failed scenarios using DVE/Verdi
• The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.
• Periodically publish technical papers and/or file patents on the feature updates/innovation carried out
• In addition, the candidate should have excellent oratory and written communication skills in English, should be a team player and possess good problem solving skills and show high levels of initiative.

Job tags

Salary