7Rays Semiconductors India Private Limited
Location
Bangalore | India
Job description
Experience- 4 to 8 years RTL to Netlist Synthesis experience in Genus and Design compiler is a basic requirement. Meet all the DC/Genus exit criteria including PPA meeting and constrains validation Floorplan based Synthesis knowledge like DCG etc is must Working with RTL designer on constraints debug and feedback on constant basis is must. Prelayout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closure ECOs and final tapeout timing closure skills across corners and modes Must work RTL design team, PD team and HMs team for overall timing closure for SoC Primetime and Tempus knowledge is essential Leakage recovery, Vmin targets and performance v/s leakage trade-off is essential knowledge for final sign-off Deep scripting knowledge is essential Soft skills working with stake holders is must
About Company: 7Rays Semiconductors is a provider of end to end custom SoC design solutions ranging from SoC Architecture, RTL design, Design verification, DFT, Physical Design & Analog design. We are focused on providing services to top semiconductor and system companies to help them with the design of their complex SoCs. We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a strong engineering team and a proven track record of successful project executions, we are committed to excellence and innovation in SoC Design, Development and deployment of customers’ products.Job tags
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