...verification
-Familiar with process to create good requirement spec and providing valuable feedback
-Diagnosis, troubleshooting and testing of frond end eda tools internally & customer issues as required
-Revi...
Job Description :- Expertise in the verification of IP or SOC cores.- Visa sponsored for candidates with 5+ years of relevant expertise- Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implem...
Job Description :- Expertise in the verification of IP or SOC cores.- Visa sponsored for candidates with 5+ years of relevant expertise- Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implem...
Skills: AMS & wreal modeling, SV modeling and Testbench development, spectre/spice simulations, Basics of UVM, python and perl scripting
Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks
· Very Good experience in...
3 to 5 years of work experience in ASIC/SoC Design.
Experience in Logic design / RTL coding is a must.
Experience is SoC design and integration for complex SoCs is a must.
Experience in Verilog/SystemVerilog is a must.
Experience in Multi...
Company Overview:
Coders Brain Technology Pvt. Ltd. is a leading firm in the IT Services and IT Consulting industry.
Role and Responsibilities:
We are looking for an experienced FPGA Design Engineer with 6 to 12 years of experience in FPGAb...
Skills: AMS & wreal modeling, SV modeling and Testbench development, spectre/spice simulations, Basics of UVM, python and perl scripting
Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks
· Very Good experience in...
Job Title Verification Engineer
Experience Level 5 10 yrs
Location Hyderabad
Qualification B.Tech / M.Tech / BE / ME
1. Good verification skills (Verilog system Verilog).
2. Strong Knowledge of UVM methodology with hands on experience ...
1. Proficient in Verilog coding and RTL design, data path designs, 2. Knowledge of RTL checks ex- LINT, SDC, CDC
3. Familiar with synthesis flow and timing constraints
4. Experience in writing Verilog testbench and running simulations.
5. Desir...
