Hiringlabs Business Solutions
Location
Bangalore | India
Job description
3 to 5 years of work experience in ASIC/SoC Design.
Experience in Logic design / RTL coding is a must.
Experience is SoC design and integration for complex SoCs is a must.
Experience in Verilog/SystemVerilog is a must.
Experience in Multi Clock designs Asynchronous interface is a must.
Experience in using the tools in ASIC development such as Lint and CDC.
Experience in Synthesis / Understanding of timing concepts is a plus.
Experience in ECO fixes and formal verification.
Should have knowledge of AMBA protocols AXI AHB APB SoC clocking/reset architecture.
Excellent oral and written communications skills.
Proactive creative curious motivated to learn and contribute with good collaboration skills
rtl coding,cdc,asic development tools,rtl,lint,asic,ahb,synthesis,written communication,multi clock designs,logic design,system-verilog,asynchronous interface,eco fixes,apb,oral communication,formal verification,amba protocols,axi,soc clocking/reset architecture,soc design,system verilog,verilog,collaboration
Job tags
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