Design verification Engineer

Location

Provincia di Reggio nell'Emilia | Italy

Job description

o : RTL Design Verification Engineer

: 5 Years

: Bangalore/Bhubaneswar

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• Develop and execute verification plans for complex RTL designs.
• Perform functional and performance verification of design blocks.
• Collaborate with crossfunctional teams to ensure successful IP component integration.
• Contribute to enhancing verification methodologies and best practices.

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Bachelors or masters degree in electrical engineering/Electronics & Communication Engineering or related field.

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Minimum of 5 years of experience in RTL design verification.

Proficiency in Verilog/ System Verilog and experience with industrystandard verification methodologies (OVM/UVM).

Strong understanding of ASIC design flow and verification techniques.

Excellent problemsolving and debugging skills.

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• Experience with formal verification tools and methodologies.
• Familiarity with scripting languages (e.g. Python Perl) for automation tasks.
• Knowledge of industrystandard protocols and interfaces (e.g. PCIe AXI AHB).

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• Opportunities for professional growth and career advancement.
• Vibrant and inclusive work culture that values collaboration and innovation.

If youre ready to take your career to the next level and contribute to groundbreaking projects we want to hear from you!

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: Please name the file in the following format: Your Full

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design,verilog,rtl design,communication,universal verification methodology (uvm),semiconductor device

Job tags

Salary