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Location

Erie, PA | United States

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Job description

Duties: Location: Bay Area CA (Remote) Experience level: 10 Years Mandatory Skill: Arteris NoC (Network on Chip) RTL generation or based on any other NoC tool. Digital design principles in SoC and/or IP development high speed PCIe designs and protocols experience with Industry standard interface protocols such as AXI APB etc Responsibilities: Proficient in Verilog/System Verilog coding constructs. Knowledge of frontend tools (Verilog simulators Connectivity tools CDC checkers low power static checkers linting) Experience with high speed PCIe designs and protocols. Experience with Industry standard interface protocols such as AXI APB etc. Experience with ARM Fabric IPs. Experience with IPXACT. Understanding of Computer Architecture fundamentals. Ability to write scripts using Python Tcl Perl etc. Experience in EDA tools such as VCS VCLP Spyglass Lint Questa CDC Fusion Compiler Design Compiler Genus. Proficiency with UPF (Low power intent) Proficiency in clock crossing techniques. Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.

Skills: Location: Bay Area CA (Remote) Experience level: 10 Years Mandatory Skill: Arteris NoC (Network on Chip) RTL generation or based on any other NoC tool. Digital design principles in SoC and/or IP development high speed PCIe designs and protocols experience with Industry standard interface protocols such as AXI APB etc Responsibilities: Proficient in Verilog/System Verilog coding constructs. Knowledge of frontend tools (Verilog simulators Connectivity tools CDC checkers low power static checkers linting) Experience with high speed PCIe designs and protocols. Experience with Industry standard interface protocols such as AXI APB etc. Experience with ARM Fabric IPs. Experience with IPXACT. Understanding of Computer Architecture fundamentals. Ability to write scripts using Python Tcl Perl etc. Experience in EDA tools such as VCS VCLP Spyglass Lint Questa CDC Fusion Compiler Design Compiler Genus. Proficiency with UPF (Low power intent) Proficiency in clock crossing techniques. Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.

Education: Bachelors Degree

Required Skills: VERILOGEDA TOOLSPERLTCLPYTHON
Additional Skills: NOCCODINGSOCPCI EXPRESSARMIPSDIGITAL DESIGN

Minimum Degree Required: Bachelors Degree
Hours Per Day: 8.00
Hours Per Week: 40.00
Languages: English( Speak Read Write )
Department: Regional Recruiting Services : 7134
Job Category: IT

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Salary