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Location

Santa Clara, CA | United States

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Job description

Job Position: RTL Engineer (PLL Design Team) C2C

ATTN: No VISA Transfers/OPT or CPT



Responsibilities:

- Defining, specifying, modeling, and implementing RTL for advanced PLL IPs.
- Analyzing complex digital design problems and proposing solutions.
- Developing Verilog RTL and Functional Behavioral Models.
- Driving\/developing ASIC design flows and scripts.
- Creating microarchitecture specifications.
- Working with Design Verification and Physical Design teams to ensure functional correctness and proper implementation of the design.
- Delivering improvements, optimization, and power-saving enhancements.
- Supporting silicon bring-up and diagnostics.

Requirements:

- Excellent analytical and critical thinking skills.
- Attention to detail.
- Ability to take initiative and drive tasks independently.
- Strong communication skills.
- Enthusiastic team player.
- Ability to mentor and guide junior engineers.
- Relevant academic background (Master's degree preferred) with at least 5 years' progressive experience.

Preferred Experience:
- Proven experience in analog mixed signal design from specification to successful silicon.
- Experience in high-speed interfaces (DDR, GDDR, HBM, high-speed SERDES).
- Experience in designs with multiple power and clock domains.
- Experience in using industry-standard ASIC CAD tools (simulation, synthesis, STA, CDC, UPF, power estimation).
- Experience in advanced semiconductor technologies (preferably FinFET).
- At least 5 years' progressive experience in RTL Design.

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Salary