Sr. ASIC/SoC DFT Engineer
Location
Mountain View, CA | United States
Job description
Job Title: Sr. ASIC/SoC DFT Engineer
Job Location: Mountain View, CA - hybrid on-site 3 days/week
Compensation: $150K - $300K+ Depending on experience plus generous equity!
Requirements: ASIC/SoC, Design-For-Test (DFT), Silicon DFT, Physical Design
Our company is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. We are seeking a Silicon Design-For-Test (DFT) lead to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for leading the delivery of built-in test functions for performant and functionally accurate silicon for our products across compute, memory management, High-speed connectivity and other key technologies in leading-edge process nodes.
Top Reasons to Work with Us
1) Competitive Compensation ($150K - $300K+ Depending on Experience)
2) Comprehensive Benefits package including equity!
3) The chance to work for a small disruptive company in the AI hardware space!
What You Will Be Doing
- Own our DFT methodology and collaborate on the silicon design and physical design methodology with a scalable solution across blocks, subsystems, fullchip designs from RTL to GDS.
- Architect the DFT solution including memory testability and repair, logic test for coverage of structural and at-speed testability for very large and complex silicon using industry-leading DFT tools and flows
- Select top-level DFT control structures to drive efficient block and subsystem level DFT implementation optimizing for DFT cost and resulting coverage
- Plan and drive intermediate and sign-off reviews as well as execution progress reporting based on key metrics-tracking towards various silicon milestones including design freeze and tapeout
- Work closely with the design, verification and physical design co-owners of the subsystem/block and top-level on DFT verification and physical design considerations to deliver best-in-class performance-power-area results
- Leading design services partners and other critical third-party vendors and partners on planning and executing block-level and chip-level DFT
- Working with Operations, foundry and test partners to bring up test program on silicon and meeting all coverage goals on silicon towards production and NPI
What You Need for this Position
Bachelors (Master's or Ph.D. preferred) in Electrical Engineering, or similar with 5+ years of experience in the following:
- Architecture-to-production experience in driving DFT strategy and execution on large and complex ASICs and SOCs to production silicon
- Production-proven experience with deploying DFT at-scale for large and high-performance ASICs and SOCs in both pre-silicon implementation and post-silicon test program completion for NPI
- Project experience in collaborating with design, verification and physical design teams to structure and partition the design optimally for PPA and sign-off
- Experience in working with a third-party design services partners to deliver tapeout-ready designs with DFT
- Experience with test engineering partners and taking test programs from bring up to volume production
- Experience with FA (Failure Analysis) and debugging failures on silicon with design and verification teams
So, if you are a Sr. ASIC/SoC DFT Engineer with experience, please apply today! or send an updated copy of your resume to [email protected] for immediate consideration!
Benefits - Medical/Dental/Vision
- PTO/Vacation Days
- Equity
Colorado employees will receive paid sick leave. For additional information about available benefits, please contact Mike Vandenbergh
Applicants must be authorized to work in the U.S.
Preferred Skills
ASIC
SOC
Design for Test
Silicon DFT
DFT Verification
Physical Design
Failure Analysis
Job tags
Salary
$150k - $300k
