Verification Engineer - II
Location
Folsom, CA | United States
Job description
Verification Engineer - II
Location: Folsom, CA
Duration: 6 months, extendable
Please note: This is a 100% Onsite Role. Laptop will be issued.
You will work on the verification team for discrete graphics SoCs. The ideal candidate will have the following characteristics:
MUST-HAVE Qualifications
- Top Skills: UVM methodology, SystemVerilog, Verilog
- Can create and drive the creation of test plan and testbench architecture documents from specification
- Can generate directed and constrained random tests
- Has experience with emulation/FPGA based verification
- Expert knowledge of UVM methodology, SystemVerilog, Verilog
- Good understanding of industry standard interfaces
- Experience in reusability and portability of UVM testbenches
- Proficient at collaborating with adjacent teams, design, architecture, silicon validation
- Experienced in low power verification and power aware simulation environments
- Experienced with formal verification
- Adept at writing coverage models and defining coverage space, can analyze and improve design coverage
- Capable of building automated flows, working closely with team members to improve them.
Minimum Educational Requirement: Have a BS and 3+ years of exp erience.
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