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Location

Santa Clara, CA | United States

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Job description

We are a 400+ person computer hardware manufacturer with locations across the world!  This will be a full time role located in either of our US locations: Austin, TX / Santa Clara, CA / Ft. Collins, CO and will offer a hybrid work schedule. 

What you will be doing:

• Leading physical design of high performance designs going into industry leading AI/ML architecture 
• You'll be involved in all implementation aspects from synthesis to tapeout for various IPs on the chip
• Working closely with our front end team, understanding the chip architecture and ultimately driving physical aspects early in the design cycle
• Synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization
• Improving power, performance in the design area with RTL, evaluate synthesis, power results and timing
• Work with RTL designers to explore design options

Requirements:

• BS/MS/PhD in EE/ECE/CE/CS
• 5+ years working with PPA on high performance and low power designs
• Strong understanding of logic design fundamentals and gate/transistor level implementation
• Experience optimizing RTL for timing/power
• Block and chip level implementation

Bonus points: 

• Low power design (power gating, multi-Vt, voltage scaling)
• Python/Shell/Perl/Tcl
• CPU knowledge or AI/ML Accelerator micro architecture
• Exposure to DFT

Benefits

• Strong pay
• Huge room for career growth
• Full benefits
• Hybrid work schedule
• Opportunity to work in either location: Austin, TX / Santa Clara, CA / Ft. Collins, CO

Colorado employees will receive paid sick leave. For additional information about available benefits, please contact Bobby June

Applicants must be authorized to work in the U.S.

Preferred Skills

Physical Design

Chip Architecture

Low Power

RFL

Synthesis

Timing

Power

Voltage

Python

CPU

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Job tags

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Salary

$170k - $200k