Location
Cedar Rapids, IA | United States
Job description
Title - Sr FPGA Engineer
Location Cedar, Iowa (remote)
Experience 7 to 10 years
Job Description:
- 7+ years of FPGA design principles.
- 5+ years Working with Xilinx/Altera FPGA.
- Look for SV/UVM experience is must
- Must have done RTL synthesis, constraints design, timing closure
- Must have experience with design and test bench development to verify the RTL design using Verilog, VHDL or SV/UVM
- Experience with DO-254 preferred
- Must be able to develop Communications and fault logging CPLD/FPGA design.
- Must have experience in developing PHAC, HDP, Requirements capture, design documentation
- Must have hands-on experience with Cadence or Synopsys tool, Microsemi Libero or Xilinx Vivado tool.
- Familiar with SCRUM/Sprint JIRA process.
- Qualification: BE
Job tags
Salary