Location
Palo Alto, CA | United States
Job description
Please Note: As of July 22, 2021, our team will require that all candidate submissions include a LinkedIn profile. Please do not submit any candidates that do not have a LinkedIn.
NA has a client that is seeking DV Engineers Here's what you will do. Define and review verification and validation test plans at the unit, subsystem and full chip levels. Verify DFT through writing testbenches, scoreboards, assertions, and running netlist tests. Verify DFT through generating automated test patterns using industry tools. Integrate TAP, Efuse, and other controller IPs into our designs. Integrate and work with tools and VIPs to stress-test our DFT for various protocols. Develop and maintain regressions, tools, infrastructure, and methodology. Post-silicon validation brings up and production ramp.
Additional Details:
- Create Verilog/System Verilog test benches to verify various DFT features in RTL such as SSN, compressed and uncompressed scan, memory BIST, JTAG, and boundary scan at block and SoC-level.
- Verify top-level features such as power-on self-test, clock observation, clock stop and scan dump.
- Run DV regressions and analyze coverage, triage and debug failures.
Required Skills : . BS or MS in computer science, computer engineering, or electrical engineering 10 years of work experience in designing, verifying, and validating complex hardware systems. . Solid programming skills in C/C , Verilog, System Verilog, UVM, assembly, and Python. . Experience with writing directed and random test cases. . Experience with design verification and validation methodologies and strategies. . Experience with advanced design-for-test (DFT) design concepts and tools. * Experience in general design verification methodology, regressions, simulation and debug tools * Expertise in Verilog or System-Verilog * Working knowledge of scripting languages such as TCL, python (or another scripting language such as Perl) * Knowledge of DFT techniques and features for digital logic (NA9.1, NA9.6, 1NA7, 1500, Scan, On-chip clock control, Test compression, Logic Built-in-Self-Test, Boundary scan) required * Experience with Tessent tool flows for DFT RTL insertion and ATPG is required * Experience in ATPG, coverage analysis, gate simulations and mismatch resolution is required . Good communication skills, and a team player. . Able to work independently in a fast-paced team and environment Desirable experiences: . Deep knowledge of system architecture including CPU, GPU, interconnects, memory sub-systems, HBM/DDR. . Experience with boot, reset, and clocks/PLLs. . Experience with gate level simulation, Xprop, JTAG, scan/boundary scan, Efuses . Experience with Tessent, MBIST, LBIST, ATE, ATPG. . Experience with integrating controller IPs and VIPs. Prior work experience with vendors and industry tools is a plus. . Post-silicon SLT bringup and validation experience is a plus
Rank :B1
Requested Date :2024-02-07
Job tags
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