ASIC Design Verification Engineer- System Verilog UVM
Location
Fremont, CA | United States
Job description
If you are a Design Verification Engineer- System Verilog UVM- ASIC with experience, please read on!
What You Will Be Doing
(THIS POSITION REPORTS TO MILPITAS 3 DAYS A WEEK AND IS PARTIAL REMOTE, SIGN ON BONUSES ARE AVAILABLE TO HELP MOVE TO THE AREA)
" Overall, responsible for verification of ASIC designs To include such things as:
o Design Verification Implement test benches in UVM and Sytem Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design team.
o Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible for Debugging Designs for High throughput, Low Latency of Pipeline and Dynamic Power Management at full system level.
o Setup Verification Regression suites at RTL Level & Corresponding Netlist Level after Synthesis to test any/all Corner case conditions.
Necessary Qualifications:
" BS or MS in Computer Science or Electrical Engineering.
" 5+ years of industry experience bringing silicon ICs into high volume production.
" Must have strong experience with UVM.
" Must have a full chip verification experience
" Experience of leading a single project.
" Knowledge of industry standard interfaces. Extensive Familiarity with Verilog, Simulation tools & demonstrated ability to debug Problems & Troubleshoot in Real Time.
" Sound knowledge of ARMv8, interconnect, memory coherence and memory architectures
" Familiarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verification)
" Expertise in writing Perl / Python , awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals USB, PCIe, MIPI, SDIO, PCI E & DDR Controllers.
" Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation
" Experience with low-level programming of systems in C/C++.
" Experienced in writing scripts in languages such as Perl, Python, and Tcl.
" Functional understanding of constrained random verification process, functional coverage, and code coverage.
" Low power verification UPF
" Team player with excellent communication skills and the desire to take on diverse challenges.
" Customer interaction
Other Qualifications:
" Good knowledge of low power camera and imaging systems is a plus
" Experience with formal verification tools is a plus.
" CPU Security, Secure boot, Secure JTAG
" Familiarity with ARM architecture
" Familiarity with scripting/programming with Perl/Python, Tcl, C/C++
What You Need for this Position
- Design Verification Engineer
- System Verilog UVM
- UVM
- System Verilog
- Design Verification
- Universal Verification Method
- ASIC
- RTL
- Chip verification
So, if you are a Design Verification Engineer- System Verilog UVM- ASIC with experience, please apply today!
Benefits Health Benefits
- Medical Plans (PPO and HMO)
- Vision Plan
- Dental Plan
- Employee Assistance Program (EAP)
- Flexible Spending Account (FSA) benefits
- Long-term and short-term disability insurance
- Life insurance and AD&D
Retirement Benefits
- Lucrative 401K Matching
- 401(k) Plan
- Roth 401(k) Plan
Other Benefits
- PTO, Paid Vacation
- Sick Time
- 15 Paid Holidays
- Employee Referral Bonus
- Team Building Events
- Charity and Community Involvement
- Great Culture and Work-life Balance
- Coffee, Drinks, and Snacks Available for Employees
Applicants must be authorized to work in the U.S.
Preferred Skills
Design Verification Engineer
System Verilog UVM
UVM
System Verilog
Design Verification
Universal Verification Method
ASIC
RTL
Chip verification
Job tags
Salary
$140k - $215k
