Job Description and Requirements
Senior STA Engineer
Responsibilities:
We are looking for STA Engineers with proven Signoff Static Timing Analysis skills who can independently signoff timing closure of a design. We are looking for dynamic, ...
...Looking for Block Level Physical Design/ Verification for a 3nm/5nm. Available to start in Two Weeks
The candidate will be executing P&R tools on a high-speed digital semi-custom layout
~ Candidate will assi...
Be part of the Cadence High-Speed SerDes PHY IP Front end Design team responsible for - -Defining microarchitecture of digital blocks involving microcontroller-based designs to meet specifications, optimized for performance metrics of timing, area, ...
Job Description
We are hiring for Synthesis & STA Individual engineer with good understanding on constraints & who is a more independent problem solver with decent knowledge on STA signoff requirements .
Responsibilities:
Work on challenging DDR P...
We are seeking a highly motivated Synthesis and STA Engineer to join our team.
The successful candidate will be responsible for performing Synthesis and STA timing closure for our cutting-edge microchip designs.
The ideal candidate will have a...
...Minimum 3+ year experience. Physical Design for Noida Location • Technologies Below 14nm……10nm,7nm, latest one .3nm
• Block level floor planning and IR drop analysis.
• Block level timing closure with sign off S...
Job Role : Physical Design Engineer/Lead
Experience : 4-15 years
Location : Bangalore
Requirements:
· Experience in Timing Closure/ECOs on block level and chip level in a highly complex clocking environment
· Good knowled...
...and deliverables eg: Lint, CDC, Synthesis, T iming constraints , LEC ATPG
Experience and ability to bring complex SOCs into the physical world and into production
#SoC Integration #ARM #Synthesis #Timing Co...
Looking for Block Level Physical Design/ Verification for a 3nm/5nm.
Available to start in Two Weeks
The candidate will be executing P&R tools on a high-speed digital semi-custom layout
Candidate will assist the DE Leads ...
Looking for Block Level Physical Design/ Verification for a 3nm/5nm.
Available to start in Two Weeks
The candidate will be executing P&R... ...tools on a high-speed digital semi-custom layout
Candi...
