Perform hands-on physical design and physical verification tasks across projects in advanced process nodes.
Manage project-specific ASIC development flow setup and maintenance.
Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and LEC for block level and full chip flat/hierarchical designs. Coordinate full chip physical design and verification activities.
Physical verification tasks include creating setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes in the physical design database.
Ensure correct IP and pad-ring integration in block and flat designs.
Mentor junior PD/PV team members and oversee their tasks.
You will be reporting to ASIC Design Director.
What you'll Need:
Minimum 8+ Years of experience in ASIC/ SoC Physical Design.
Skills - have working experience in advanced FinFET node designs.
Experience with Cadence PnR/STA tools and Calibre; good scripting/automation skills is a must.
Education - B. Tech /M. Tech in Electronics Engineering.
Hybrid work environment
Competitive Compensation Package
Restricted Stock Units (RSUs)
Hybrid Working Model
Provisions to pursue advanced education from Premium Institute, eLearning content providers.
Medical Insurance and a cohort of Wellness Benefits
