Microchip Technology
Location
Secunderabad | India
Job description
Candidate will join the Systems Validation Group to drive the system level validation of interfaces and architecture features for the FPGA.
Create System and FPGA designs to exercise all the use models targeted for each product mimicking end applications in a customer setting.
Write system and product level validation plans for new and existing silicon products and projects; execute per plan, record and communicate results
FPGA prototyping and emulation. Understanding spec., writing emulation plan and executing per plan. Record and communicate results.
Understand hardware architectures, use models and system level design implementations required to utilize the silicon features.
Be an effective contributor in a cross-functional team-oriented environment.
Write high quality code in Verilog, VHDL and C code for embedded processors. Maintain existing code.
Learn new system designs and validation methodologies. Understand FPGA architectures.
Requirements/Qualifications:
Hands-on systems level design, debug and validation experience with serdes based protocol, worked with PCS/PIPE interface and controller, DMA use cases.
FPGA architecture, design flow(Vivado / Quartus / Libero / Diamond) and timing closure
Design with RTL coding in Verilog/VHDL and Verification of RTL
Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools
Basic knowledge of embedded processors such as ARM Cortex-M3 or RISC and familiarity with AMBA protocols APB, AHB, AXI, ACE
Knowledge on embedded software C/C++ programming and bare metal application development and debug
Board level debug skills using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (eg Synopsys Identify, Xilinx Chipscope)
Working knowledge of SERDES CTLE and DFE circuits preferred
Experience on NOC based processor system interface with protocol controller is a plus
Excellent verbal and written communication skills in English
Experience working with memory interfaces and training ip on DDR4/5, LPDDR4/5 memories is a plus
Travel Time: 0% - 25%
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