Design Verification Engineer
Location
Hyderabad | India
Job description
Title: Design Verification Engineer
Duration: Full Time
Location: Hyderabad
Experience: 4
Description :
- Experience in Verification of IP/SOC/Design
- Experience in UVM/SV/ test bench development
- Candidates with CPU-Core, Peripherals, Low Power Verification or Modem domain, debug skills, DV Integration are preferred.
- Preferably with exposure to Power Aware/GLS, RISC-V processor
- Protocols experience - PCIe/CXL/UCIe/DDR/Ethernet
- In addition Formal, Assertions, Coverage etc, Netlist simulation experience
Expertise in SV-UVM, Testbench development from scratch
Job tags
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