Senior Physical Design PnR Place and Route Engineer
Hiringlabs Business Solutions
Location
Bangalore | India
Job description
- The responsibilities will include several of the following but not be limited to:
- Performing floorplanning and routing studies and implementation at block and fullchip level
- Push down the toplevel floorplan and clock to Partition.
- IO Planning and bump planning
- Closely working with Package team and reaching Die file milestones
- Full chip and partition level timing analysis.
- Evaluate low power techniques and power reduction opportunities
- Perform clock distribution design and analysis
- Perform Physical verification activities at fullchip level.
- Drive technical activities of physical design during technology readiness design & execution
- Indepth knowledge and handson experience on Netlist2GDSII Implementation i.e. Floorplanning Power Grid Design Placement CTS Routing STA Power Integrity Analysis Physical Verification Chip finishing. Should have experience in Physical Design Methodologies and submicron technology of 16nm and lower technology nodes
- Should have experience in handling >1M instance count 1 GHz frequency designs
- Should have experience in programming in Tcl/Tk/Perl to automate the design process and improve efficiency
- Must have handson experience on PNR Suite from Cadence & Synopsys (Innovus & ICC2)
- Strong experience in Static Timing Analysis (PrimeTime SI) EM/IRDrop analysis (PTPX Redhawk) Physical Verification (Calibre).
pnr,primetime si,floor-planning,block level,low power techniques,physical verification activities,automate the design process,static timing analysis,floorplanning,frequency designs,physical design methodologies,package team,fusion compiler,improve efficiency,chip finishing,instance count,placement,die file milestones,place and route,implementation,power grid design,netlist2gdsii implementation,pnr suite from cadence,synopsys,routing studies,power integrity analysis,calibre,routing,sta,design & execution,clock distribution design,timing analysis,power reduction opportunities,innovus & icc2,cts,programming in tcl/tk/perl,bump planning,physical verification,redhawk,innovus,technology readiness,full-chip level,io planning,sub-micron technology,em/ir-drop analysis
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