Enphase Energy
Location
Bangalore | India
Job description
Own full-chip RTL integration to Synthesized netlist generation. Act as liaison with our ASIC backend design services partner.
You will be working with the Architecture IP design teams for RTL Integration, timing constraints creation, synthesis.
You will also validate the STA results on the final database delivered by our ASIC partner DFT to entitlement.
Requirements
Deep understanding and experience in SoC architecture and integration
Ability to create the timing constraints based on specificationRTL Integration of SoC/Subsystems from IPs, ability to debug the issues in logic verification, act as liaison between Design and Place and Route teams
Knowledge of all the Soft IP collateral and deliverables eg: Lint, CDC, Synthesis, T iming constraints , LEC ATPG
Experience and ability to bring complex SOCs into the physical world and into production
#SoC Integration #ARM #Synthesis #Timing Constraints #STA #DFTThis position is based in Bangalore
Credentials
Prior hands on work experience of at least15 years in Logic IP/SoC design.
Job tags
Salary
