Cadence Design Systems
Location
Bangalore | India
Job description
Responsibilities: · Complete DFT ownership of projects including: · Test architecture definition. · Identifying and implementing RTL changes for DFT. · Performing scan insertion. · Developing timing constraints for test mode timing closure. · Scan and ATPG for different fault models. · Boundary scan, ACJTAG, IEEE 1500 implementation and verification. · IEEE1687 (iJTAG) for functional manufacturing tests. · Running zero delay and timing simulations and debugging on all the above aspects. · Supporting post silicon bring up. · Interacting with customers on DFT aspects and support Marketing & Pre-Sales team. · Experience working on very high speed and low power designs.
Requirements/Qualifications: · This role requires close interaction with multiple cross functional teams across geographies to align on project receivables/deliverables. · Mentoring junior engineers and driving innovation/automation. · BE/B.Tech/M.E/M.Tech with 7+ years of relevant work experience and strong understanding of DFT concepts and good communication skills. · Strong hands-on experience using industry standard EDA Tools. · Experience with logic simulators from one or more EDA vendors. · Experience on industry standard ATPG tools like Cadence Modus. · Experience with RTL lint tools like Jasper. · Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is required. · Programming in Perl/Tcl/Python or other scripting languages is a plus. · Experience in post silicon validation, ATE debug and support is desired. · Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop. · Good understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis are plus. · Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability.Job tags
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