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Location

Secunderabad | India

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Job description

Responsibilities :

Be a technical digital design lead for sub-system
Own the design and work with cross functional teams (IP designers, verification, physical design, timing) for execution of sub-system
Interact and participate in discussion with customers on IP integration, reviews
Over the period grow expertise on various PCIe PHY and controllers
Debug simulations independently over the period w/o help from actual IP designers and make correct decisions
Guide verification team on verification plan and code coverage
RTL quality checks – Lint, CDC, synthesis readiness
Own the delivery schedule, articulate the progress, highlight bottlenecks and get resolution from cross functional teams spread over Geo's
Qualifications :

Master's degree or Bachelor's degree in Electronics or Electrical Engineering
6+ years of relevant work experience in micro-architecture, RTL design, synthesis and STA including SDC development
Driving design flows and overall methodology
Experience in working independently and leading large complex module design
Preferred qualifications:

Experience in the design of digital logic and components in RTL, building/own the top-level integration as well as in synthesis, timing closure, and power-optimization of digital designs
Experience in coding with Verilog and/or System Verilog along with scripting languages such as Perl, Tcl, or Python
Hands on experience on Lint/CDC, SDC ownership and qualification, Timing ECO iterations, debugging in mixed-signal simulation environment, etc.
Experience in cross functional interaction with verification, DFT and physical design teams
Understanding of PCIe protocol including good knowledge on PCS and PIPE i/f

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Job tags

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Salary