ASIC Digital Design, Staff Engineer
Location
Bangalore | India
Job description
Job Description and Requirements
At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP Subsystems business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
Here we go, look for more information on Interface IP Subsystems @
We're looking forSenior ASIC Digital Design Engineer, Implementation lead to join Synopsys Solutions Group, Digital IP Subsystems Team. Come and be part of a collaborative team environment that innovates and develops the latest DesignWare IP Subsystem solutions that enable the way the world designs.Join the Synopsys Subsystems Team ! Based in our offices in Bangalore/Hyderabad, India, you will be a senior member of the Synopsys Solutions Group Subsystems team, which is developing high performance Ditital Interface IP Subsystem solutions for DDR, PCIe, Ethernet, UFS, USB and other interface protocols.
In this role,
- As aLead Implementation Engineer, you will be responsible for Subsystems timing closure on the front-end implementation flows, Work with Design the teams driving the life-cycle of the Subsystems from requirement to release phases.
Job role and Skill set:
-- Senior implementation lead role. With 10+ years of experience.
-- Proficiency with Synthesis, timing closure and industry standard tool flows like Fusion Compiler, Formality, Prime Time, DC etc.,
-- Must have an in-depth understanding of Synthesis constraints and portability from block to top level.
-- Power aware Synthesis with UPF : Define low power architecture, execute and drive UPF implementation.
-- Hands-on understanding in DFT implementation and flows is a plus.
-- Experience with Hardening projects is an additional value add.
-- Static Timing Analysis (STA) exposure is desirable.
-- Working with cross-functional teams and driving the projects to completion.
Please get in touch with us. Looking forward to talk to you !!
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