This position is for a CPU Validation Engineer within the Silicon Validation Engineering team for Ampere s best in class 64-bit ARMv8x Server Processor family
Silicon Validation Engineering Team at Ampere enables future generations of CPUs that power Cloud, Enterprise, and Data Center! The Candidate will be responsible for validating CPU intellectual property in both emulation and post-silicon environments
We are looking for sharp collaborative engineers who pay extra attention to engineering details, passionate about top quality development validation, and interested in engineering of complex leading edge projects
What You ll Do
Development of directed, random, and pseudo-random test-suites for validation in compliance with Ampere SOC s CPU Specification and system level use cases.
Development of bare-metal test bench components to enable efficient validation and debug of highly complex CPU designs, memory topologies, and mesh.
Develop execute the CPU validation plan and methodology on HW emulators and on Silicon Platform.
You will debug CPU Mesh Functional issues to identify hardware, software, design or implementation issues and develop tools to enable diagnosis and debug of those issues.
You will work with various cross-functional teams including the architecture team, software team, chip design team, design verification team to bring up new SoCs or CPU Platforms.
Investigate future roadmaps and product user documentation to understand software impact.
What You ll Bring
Strong programming experience in at least one programming language: C/C++ or Python is required.
Prior experience with device drivers, system software or firmware development is required.
Prior experience with OS/Kernel-related debug, either Linux or Windows is a plus.
Strong understanding of ARM trusted boot Firmware flow on 64-bit Arm Architectures is required.
Good CPU architecture/micro-architecture knowledge (any of MIPS/PowerPC/ARM/x86/SPARC architectures, CPU pipeline, out-of-order, superscalar, caches) is required.
Knowledge and familiarity of concepts of multi-processor coherency, cache, MESI protocol is required.
Strong understanding of MMU, Virtualization, CPU low power modes Interrupts is plus.
Strong understanding of server CPU HW platform, topologies, and multi-socket configuration is plus.
Experience in debugging/analyzing post-silicon HW/SW issues using Lauterbach Trace32 or OpenOCD debugger is required.Familiarity with pre-silicon environments such as Verification, Emulation and post-silicon Bring-Up is plus.
Self-motivated team player with excellent problem solving skills is required.
Education Experience
Bachelor s or Masters degree in Computer Science, Electrical Engineering or related fields with 4 to 8 years of related professional experience.
