Renesas Electronics
Location
Hyderabad | India
Job description
Responsibilities
In this high impact role on the team, you will have the opportunity to: Build, lead, and manage a verification team responsible for verifying multiple complex flows at the SOC, Subsystem, and/or custom IP levels Provide technical and project management guidance to the front-end development team Lead a team responsible for the full life cycle of verification, from strategy and planning to develop verification environments, test execution, collecting and closing coverage, and debugging failures to the root cause Drive innovation to improve verification effectiveness and efficiency through methodologies or tools Manage direct reports through goal setting, mentoring, coaching, career planning, and assessing performance Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity and inclusion Qualifications Required 14+ years of pre-silicon SOC/chip level, Subsystem, or IP verification experience, including 5+ years of technical verification management. Candidate must have at least a bachelor’s or master’s degree in electrical engineering, Computer Engineering, Computer Science or a related degree Preferred Experience managing a multifaceted verification organization, providing career planning, performance feedback and appraisals, and compensation recommendations. Experience as verification technical lead of an IP, Subsystem, and/or SOC for multiple full product cycles from definition to silicon, including in depth expertise in verification principles, developing testbenches, writing plans, developing stimulus, debugging failures, and coverage signoff. Verification program management experience including planning and tracking execution, mitigating discovery, and communicating progress. Demonstrated expertise in coaching, collaboration, influencing, and energizing a team via effective written and verbal communication skills Demonstrated expertise in one or more of the following: fabrics, DDR controllers, coherency, virtualization, interrupts, security, power management, reset, clocking, RAS, PCIe, CXL, USB, protocol bridges, or other complex SOC, Subsystem, or IPs, flows, and protocols Experience creating, and/or integrating test benches, checkers and stimulus using System Verilog Test Bench (SVTB), UVM and/or C.Job tags
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