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Location

Bangalore | India

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Job description

Job Role : Physical Design Engineer/Lead Experience : 4-15 years Location : Bangalore

Requirements: · Experience in Timing Closure/ECOs on block level and chip level in a highly complex clocking environment · Good knowledge of de-rates (OCV, AOCV, POCV) · Experience with EDA Tools and Methodologies for STA, STA-based ECO, Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating · Understanding of power management and UPF concepts at Synthesis/PnR/STA domains · Good scripting skills; experience in Tempus is a plus · Experience in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....) · Complex high-speed designs for edge computing applications (3.2G HBM PHY, Processor hardening for PPA analysis)

Preference : Immediate to below 1month notice.

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Job tags

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Salary