Location
Bangalore | India
Job description
Job Details: Job Description: Defines, develops, and performs functional validation for integrated SoCs, focusing on validation of IP integration, interaction between IPs, and systemlevel features. Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met. Reviews proposed design changes to assess impact on validation plans, tasks, and timelines. Develops SoC validation methodologies, validation test plans, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis. Performs silicon debug to identify root causes and resolves all functional and triage failures for SoC issues. Tests interactions between various SoC features using validation infrastructure. Develops postsilicon validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing. Publishes SoC validation reports summarizing all validation activities performed, reviews results, and communicates to relevant teams. Works with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for SoC interfaces and to meet desired product specifications. Develops content to create or increase specific IP interactions using a variety of tools and techniques (including patching techniques using microcode, firmware, or custom OS builds). Engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (e.g., simulation, emulation, FPGAs) to ensure silicon readiness. Qualifications:
Minimum Qualifications:- 3+ years of experience in relevant Pre-Silicon validation positions having gone through multiple project cycles to gather in-depth know-how.
Solid work experience in designing, verifying, and validating complex hardware systems.
Solid programming skills in System Verilog & UVM. C/C++, assembly, and Python will be a plus.
Experience with writing directed and random test cases, RTL and Gate Level validation, SDF validation, Coverage and Formal verification.
Experience with design verification and validation methodologies and strategies.
Conversant with advanced computer architecture and micro-architecture concepts.
Exposure in debugging IPs & SOCs, Memory, various protocols like PCIE / Ethernet, or other complex ASIC, die-to-die designs.
Good communication skills, and a team player.
Able to work independently in a fast-paced team and environment.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.Job tags
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