Wafer Space - An ACL Digital Company
Location
Bangalore | India
Job description
Experience - 4+ Years Well-versed with the timing closure (STA), timing closure methodologies Pre/Post-layout constraint development to timing closure Handshake with the design team and develop functional/DFT constraints IP level constraint integration Multi-voltage/Switching aware corner definitions RC/C model selection understanding Abstraction expertise like Hyperscale/ILM/ETM RC Balancing and scaling analysis of full chip clock RC Balancing and scaling analysis of critical data paths Good automation skills in PERL, TCL and EDA tool-specific scripting DMSA @ full chip and custom scripts for timing fixes
Job tags
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