Siemens
Location
Bangalore | India
Job description
Siemens EDA - Consulting and learning services organization is looking for Manager for Physical Design.
The person will be responsible for bringing up Physical design team in India and will be leading the team in India working in close collaboration with the global PD teams.
As a member of Consulting and learning services team, you will be working on doing BE implementations for world-wide customers across different domains and technologies.
Primary duties will include:
. to be involved in multiple simultaneous ASIC backend engagements to ensure that design
development makes appropriate progress.. consistent proactive analysis of both methodology and design implementation to catch issues in all stages of the design from RTL to GDS, along with in-depth technical
debug and providing guidance on critical or high-risk issues.. A hands-on approach to debug and implementation will be expected. Contributions to
methodology development will be expected.. Strong communication and interaction with both implementation partner teams and
customer teams will be required.. will also be involved in reviewing capabilities of implementation partner resources, interviewing potential engineering hires, and managing the growth of regional
Siemens engineers.Requirement:
At least 12+ years experience in ASIC backend development work, with significant experience driving large-scale hierarchical designs being mandatory. Strongly recommended to have experience managing multiple implementation teams across different time zones. Experience in driving flow/methodology development.
. Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
. Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning
. Work closely with CAD teams and involve in methodology development and improvement
. Own SoC/partition physical design activities while managing a team
Desired Skills and Experience:
o B. Tech. / M. Tech with 12+ years of experience in Physical Design
o Tool familiarity with synthesis (DC/Genus), PNR (ICC2/Innovus), LEC (Formality/Conformal), STA (PrimeTime/Tempus), PV (Calibre), power (PrimePower/Voltus/Redhawk).
o Understanding of SDC, UPF, LEF/DEF, LIB, spice, Calibre decks.
o Thorough experience in synthesis, hierarchical floorplanning, power planning, clock tree analysis and design, congestion triage, fullchip timing closure, constraint development, power optimization, LEC debug, DRC/LVS closure, IRdrop/EM closure.
o Good understanding of low power implementation techniques and static low power checks
o IO ring design and bump planning is a plus
o Experience with a variety of foundries and technology nodes from 5nm to 180nm.
o Fluency in TCL and Perl/Python.
#LI-EDA
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