Cadence Design Systems
Location
Bangalore | India
Job description
Job Description We are hiring for Synthesis & STA Individual engineer with good understanding on constraints & who is a more independent problem solver with decent knowledge on STA signoff requirements . Responsibilities:
Work on challenging DDR PHY IP & Testchip synthesis/STA in multiple tech nodes 12nm, 7nm & lower nodes across foundries. Own multiple blocks synthesis , constraints, scripts, flow updations etc… Signoff Environment document reading & update existing Environment accordingly. STA Closure for TC, IP. Contribute to design methodology, flow automation. Participate in IP release to customers and support team on standardize & document learnings. Key Skills: RTL-Netlist synthesis, STA, LEC, Verilog/VHDL, STA signoff Understanding, UPF, 7nm+ & lower Technology nodes across foundries, scripting tcl & python. Minimum qualifications: Bachelor’s degree in Electronics or equivalent practical experience. 5+ years of experience and in depth knowledge on RTL-Netlist synthesis, constraints reading , LEC. Experience on sub 7nm tech nodes. Good hands on experience on scripting tcl & python. Preferred qualifications: Experience in physical synth, Lower power DDR PHY designs. Experience in Cadence tools Genus, Tempus, Innovus, CLP & Voltus. Lower Tech node N3, Samsung N5,N4 knowledge is a plus.Job tags
Salary
