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Location

Bangalore | India

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Job description

Physical Verification – 4 to 7 years.

• Work with floorplan and physical design engineers to drive physical verification convergence.
• Should be proficient in DRC and LVS analysis at advanced nodes like TSMC5 or below.
• Good knowledge in specific areas like Antenna, ESD, ERC, LUP will be preferred.
• Working knowledge on full chip phyV will be added advantage.
• Prior work experience on Full Chip RDL like IO/PAD Ring routing will be preferred.
• Understanding on multi voltage regions will be preferred.
• Experience: Minimum 4- 7 years experience on Physical Verification exclusively. Don't club
other experience.
• Tools: Expertise in Calibre and ICC2 tools.
• Scripting will be preferred.
• Scripting inside Calibre tool will be added asset.

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Job tags

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Salary