Wafer Space - An ACL Digital Company
Location
Bangalore | India
Job description
Work Location - Bangalore
3+ years of experience
Technical Skills:
- Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure
- Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM
- Must have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification, IREM)
- Well versed with the timing closure (STA), timing closure methodologies
- Good Understanding of DRC, LVS, ERC, and PERC rule files for lower-tech node layout verification
- Experience in lower tech node ( • Good automation skills in PERL, TCL, and EDA tool-specific scripting
- Able to take complete ownership of Block/sub-system for a complete execution cycle
Job tags
Salary
