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Location

Bangalore | India

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Job description

Design Verification Lead Job Location: Hyderabad / Bangalore. – 100% Work from Office - No hybrid. Experience: Min 10+ years to 18 years.

Skills:

Block level, full chip verification experience using SV, UVM, RAL, Assertions. Hands on experience in PCIe and memory controllers DDR/NVMe.

Roles and Responsibilities 8yrs yrs of Experience in developing TB & TB components for block level and full chip level verification. Experience in creating Test plan, writing Test cases Proficient in System Verilog \Verilog Proficient in writing Assertions UVM based Methodology with strong understanding of OOPS concepts Good knowledge of Digital Fundamentals Good knowledge of Scripting (Perl, Shell), C language Familiar with different aspects of IP development: micro-architecture, RTL & TB implementation, Test plan, Functional coverage, Code coverage and regression Strong Simulation & Debugging skills Strong analytical skills with attention to detail Excellent written & verbal communications skills. Knowledge of protocols such as PCI-Express, Rapid IO, NVM Express, NAND,CXL and DDR/ LPDDR Experience implementing directed and random test cases. Very good leadership skills. You will be a key player in IP development for Memory/Wired-Interconnect/ Networking/Mobile/ Video Develop BFMs, Drivers, Monitors and Scoreboard for the test bench in System Verilog.

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Job tags

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Salary