SiFive
Location
Bangalore | India
Job description
Defining the power budget/spec for IPs, and coming up with new micro architecture initiatives, rolling up of the power numbers and maintaining the chip power dashboard for various applications.
Use existing workflows to analyze Energy and make high ROI RTL modifications to improve Energy.
Work with logic teams to determine the correct functionality or enhance functionality for power reduction.
Select and run a wide variety of workloads for power analysis.
Develop IP power model on new architecture design, providing power data for performance/power/area treads-offs.
Work with multi-functional teams on improving power modeling.
Requirements:
Bachelor or Masters degree (or equivalent experience)
10+ years of experience with silicon power management architecture techniques.
Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre - Silicon Validation teams for improving test content
Functional knowledge of Idle/Sleep Power states (C-States), Dynamic Perf states (P-States) and reset and retention.
Knowledge of multi cluster architectures and power management.
Proficient on running silicon content on pre-silicon platforms such as emulation or FPGA for power measurements and validation
Deep understanding of power principles and tradeoffs.
Strong interpersonal and teamwork skills.
Job tags
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