Manager - Physical Design Engineering
Analog Devices, Inc. (ADI)
Location
Bangalore | India
Job description
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY22 and approximately 25,000 people globally working alongside 125,000 global customers, ADI ensures today's innovators stay Ahead of What's Possible.
Analog Devices, Inc. is looking for a Manager - Physical Design to join our Digital Business Unit Teamin Bengaluru, India, location.
About ADI:
Analog Devices, Inc. is a leading global high-performance analog technology company dedicated to solving our customers' most complex engineering challenges. We play a critical role at the intersection of the physical and digital world by providing the building blocks to sense, measure, interpret, connect, and power devices and systems. We design, manufacture, test, and market a broad portfolio of solutions, including integrated circuits (ICs), software and subsystems that leverage high-performance analog, mixed-signal and digital signal processing technologies. We embrace a culture of innovation and collaboration to push the state of the art.
Digital IC Design at ADI:
ADI has long been considered the industry leader in high performance analog/mixed signal semiconductors, and we specialize in bridging the real word to the digital world: what is increasingly referred to by the technical community as 'the edge'. Our Digital Design engineers are responsible for developing digital designs that will meet all specifications, work flawlessly in a product team's system and be optimally manufacturable and testable.
Position Overview:
The Digital Business Unit is seeking a motivated, experienced Physical Design Manager to provide support to our Processor Business Unit (PBU) located at ADI's Bangalore site, India. The Processor BU is a growing group of creative, focused engineers developing the next generation processor platforms for intelligent edge applications. These platforms range from ultra-low power sensor MCUs, real-time signal chain processors for control systems to application stack processors running Linux. Come be a part of a highly skilled team with many opportunities for career growth.
Roles & Responsibilities
- Responsible for Physical Design schedule planning, delegating, tracking the execution of PNR & signoff tasks which includes STA/IR-RV/LEC/Low power/Physical verification & any other custom signoff based on SOC needs.
- Synthesis of RTL, STA, LEC, Power Analysis at Partition and SOC level
- Demonstrate a strong cross functional working ability across architecture/design/dv/dft. Understand their problems & provide solutions across SOC spectrum which results in better SOC & integration schedule.
- Strong Work experience in Hierarchical full chip planning.
- As Technical Manager drive Technology Node/Metal stack identification, IP/Vendor selection for the project meeting cost, power and performance needs of the SOC.
- Deep understanding in submicron nodes & design challenges.
- Hierarchical Full chip/ Subsystem planning, floor-planning & Integration.
- Custom clock tree [Htree/Mesh] building for processors designs.
- Full chip STA constraints generation, STA setup, & eco generation, working with technology/product teams & defining the STA OCV, DVFS voltages & IR-RV corners.
- Low power implementation strategy planning & defining the same for SOC/SS.
- Understanding the package/platform team needs & deliver the necessary collaterals from SOC.
- Physical Design CAD development expertise in lower nodes 16nm TSMC FinFET.
- Actively track and proactively communicate status to team and management using Agile development practices
Required Skills/Experience:
- Multiple tape-out experience in lower TSMC nodes preferably 16nm/7nm/5nm/N3E TSMC FinFET nodes.
- Expertise in block level execution which includes synthesis, Lower power aware Place and Route, Power Domain/Voltage island, Level shifter/Isolation custom planning, CTS, Timing closure, physical verification, EM/IR , LEC, VCLP and block level timing/function eco generation
- Experience in Synthesis , STA and APR at partition /SOC levels
- Experience with Full chip execution tasks which includes Bump planning, pad ring planning, full chip planning , collateral generation and integration, Top level PG/custom reference signal routing, Full chip CTS mesh or Htree, Full chip Timing closure, Full chip physical verification, Full chip EM/IR , Full chip LEC, Full chip VCLP and Fucll chip upf/sdc creations and full chip timing
- Excellent communication skills, ability to work within a cross-functional, global team
- Experience using Cadence digital implementation tools (Genus, Tempus, voltus) and calibre physical verification tools would be a bonus.
- Strong automation skill expertise in TCL/perl/python is an added advantage.
Minimum Qualifications:
- Bachelor or master's degree in Electronics Engineering/Electrical engineering/Computers or in relevant domain
- 10+ years relevant experience
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
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