Vitestork Consulting Private Limited
Location
Secunderabad | India
Job description
.3+ years of professional experience in physical design, preferably with high performance designs.
.Experience in minimum one of the Full Chip Chip Integration activities such as Full Chip Floor Planning, Power Planning , Bus Planning, Full Chip timing, Full Chip Reliability and Full Chip Physical Verification is desirable.
.Experience in FEC,VCLP.
.Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages.
.Experience in developing PD metrics dashboard scripts for QOR tracking is a plus
.Experience in modifying STA constraints to check timing closure feasibility
.Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets
.Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm
Job tags
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