ASIC Digital Design Engr, Staff

Location

Secunderabad | India

Job description

• We re looking for to join Synopsys Solutions Group, Digital IP Subsystems Team
• Come and be part of a collaborative team environment that innovates and develops the latest DesignWare IP Subsystem solutions that enable the way the world designs

In this role,

• As a , you will be responsible for signing off on Subsystems Verification, working closely with the Design leads, Architect the test bench, author Sign-off on the Test Plan, test environment, driving the life-cycle of the Subsystems from Verification requirements to release phases.

Requirements :
--- Knowledge of one or more of protocols AMBA (APB, AXI, CHI), DDR/PCIe/Ethernet/USB/UFS and other interface protocols.
--- Programming skills such as System Verilog, TCL, Perl or Python.
--- The ability to work independently, precisely and to drive innovation
--- The ability to extract detailed requirements from high-level specification
--- Good communication skills.

-- Understand the Subsystem requirements/specification and author the Verification Plan
-- Develop the SV UVM Test Environment, Own bring up the test cases by coordinating with other Verification team members
-- Drive the Verification closure of Subsystems with quality metrics.
-- Closely work with Design Leads and own/drive the verification signoff.
-- Hands-on/Lead experience on Subsystem Verification.
-- Verification experience and debug skills of IP cores and/or Subsystems and/or SOC RTL designs .
-- Experience in developing System Verilog, UVM or similar HDL based test environments .
-- Experience in developing and implementing test plans, extracting verification metrics, developing BFMs and similar verification components .
-- Obsession with quality and finding bugs .

Job tags

Salary