As a Senior Physical Design engineer, you will contribute to all phases of physical design of complex blocks, sub-systems (PCIe, Ethernet, ARM CPU, GPUs, USB, DDR, others) design from RTL to delivery of final GDSII.
Synopsys Design Services team works on implementation of critical and timing-challenged Block PDs that seamlessly integrate into product innovations involving applications of data centers, storage, networking, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles.
Clients across the globe partner with us for mission-critical data communication, using our innovative EDA tool suite, industry-leading IPs, enabling the next generation digital technologies.
What Youll Do:
Perform hands-on physical design implementation using Synopsys tools (DC, ICC2, FC, PT) and physical verification tasks (ICV, ICWB) in advanced process nodes of 5NM, 3NM, 2NM.
Develop project-specific design flow setup to perform PNR STA tasks.
Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and Formality for block level and subsystem-level flat and hierarchical designs.
Physical verification tasks include creating ICV setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes in the physical design database.
You will be reporting to SoC Design Manager
What Youll Need:
Minimum 6 Years of experience in SoC Physical Design
Skills - hands-on working experience in advanced FinFET node technologies.
Experience with Synopsys PnR/STA tools and ICV; good scripting/automation skills is highly desired.
Education - B. Tech /M. Tech in Electronics Engineering
