Location
Bangalore | India
Job description
Position Name : STA
Experience Required : 6 - 9 years
Location : Pan India
Notice Period : Immediate - 15 days
JD'S :
Desirable to have exposure in full chip implementation
Tool Experience: Design Complier, Fusion Complier/ICC-II, ICV, Conformal LEC, StarRCXT, Primetime, Candence Innovus
4-8 years experience in Static Timing Analysis & Timing closure
Strong Fundamental in STA and Tools like Primetime (SNPS)/ Cadence Tools
Work closely with cross-functional and PD teams to review full chip, sub system and partitions level Static Timing Analysis (STA)
Strong Understanding of Device physics to take call on DRC and Fixing Timing ECO.
Must have Constraints Understanding & should be well capable to understanding design Sanity.
Must have been exposed to full flow of Timing Signoff.
Scripting knowledge of TCL/PERL.
Job tags
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