Tech Mahindra Cerium Pvt Ltd
Location
Kochi | India
Job description
Hiring for DFT Experience: 4-12yrs Location:
Kochi/Trivandrum/Bangalore/Vizag/Ahmedabad · Experience in defining / understanding DFT Architecture / Microarchitecture features of a block, subsystem or SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST) · Good Working Experience in DFT Implementation – · Scan Insertion · ATPG – Pattern Generation and Simulations (Stuck-At, At-Speed, Path-Delay) and · Scan Compression · Good Working Experience in Coverage Analysis, Improvement & Closure, DRC Cleanup · Good Working Experience with GLS Timing Simulations – Diligently debug & Resolve Test Pattern issues · Validate Implemented DFT-Structures and ensure Design Quality before Tape-In · Work closely with RTL Design Team to ensure DFT design rules, quality and guidelines are met, and to ensure maximum Test Coverage · Work closely with Physical Design and STA teams to ensure correct DFT-Implementation and DFT-Timing Closure · Collaborate with post-silicon and manufacturing team to verify the feature on silicon, support debug requirements · Working Experience on MBIST Insertion & Validation is an added advantage · EDA Tools Expertise : · Synopsys DFT Compiler, DC Compiler, Spyglass DFT, TestMax/TetraMax, VCS / Verdi Compilers · Tessent DFT advisor, Test Kompress/Fast Scan, QuestaSim · Please share your profile to [email protected] for further discussion.Job tags
Salary
