Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer
As PE Layout Design, the candidate will be reporting to Layout Manager and is a Full-Time position
The MIC BU Layout team is a high-performance team gets involved in the complete development cycle starting with requirements, die area estimate, chip level floorplan, power, package discussions, execution of block level layouts, integration, physical verification, Database Transfer, e-Job review, and post-silicon support to multiple mixed signal designs which cater to market and revenue driven memory interface chips at Rambus Technologies
Responsibilities
Should lead a team of 6 to 8 members and will be responsible for execution of the assigned project/program.
Responsible for providing technical guidance to the team and coordinating with project functional groups (Design, PNR, CAD, Foundry etc.) for layout deliverables.
Should have strong collaboration with Analog Designers across the globe to solve challenging problems.
Working on layout design of owned blocks with Cadence Virtuoso XL.
Working on block and top-level/sub-hierarchy level layout verification with Calibre.
Extensive Top/Chip level layout experience
Familiarity with various Tape out procedures, Physical verification for tape out (LVS, DRC, Density, Extraction, EM).
Expertise in standard layout practices such as Layout matching, parasitic, noise & noise isolation, supply consideration, latch up, shielding, Well s substrates and Isolation.
Strong fundamental knowledge in semiconductor device physics, cross-section, and construction
Strong fundamental knowledge in layout principles, IC reliability, and failure mechanisms
Qualifications
B.Tech/BE with 10 to 14 years of relevant layout experience.
Should have experience in doing layouts for process nodes from 40nm, 28nm, 22nm, FINFET nodes (16nm, 12nm, 7nm).
Should have exposure to chip level floor plan, power grid, good understanding of EM/IR at chip level.
Sound knowledge of pad placements, ESD/Latchup requirements.
Sound knowledge of device matching, double pattering and other layout dependent effects. Knowledge of scripting on SKILL, PERL is an added advantage.
Familiarity with package selection procedures and design checks.
Good team player with self-motivation and excellent communication skills
