We are looking for Senior ASIC Digital Design Engineer to join Synopsys Solutions Group, Digital IP Subsystems Team
Come and be part of a collaborative team environment that innovates and develops the latest DesignWare IP Subsystem solutions that enable the way the world designs
Join the Synopsys Subsystems Team, Based in our offices in Bangalore/Hyderabad, India, you will be a senior member of the Synopsys Solutions Group Subsystems team , which is developing high performance Digital Interface IP Subsystem solutions for DDR, PCIe, Ethernet, UFS, USB and other interface protocols
In this role,
As a Lead Design Engineer , you will be responsible for RTL Design, Architecting & Integrating the Subsystems, signing off on the front-end implementation flows, Work with Design and Verification teams driving the life-cycle of the Subsystems from requirement to release phases.
Requirements : - Knowledge of one or more of protocols AMBA (APB, AXI, CHI), DDR/PCIe/Ethernet/USB/UFS and other interface protocols. - Programming skills such as System Verilog, TCL, Perl or Python. - The ability to work independently, precisely and to drive innovation - The ability to extract detailed requirements from high-level specification - Good communication skills. Lead Design Engineer position will require you to: - Understand the requirements and Architect the Subsystems based on the requirements . - Integrate the RTL and drive the Design tasks to complete the Subsystem - Sign-off on the front-end implementation flows like Synthesis timing closure using DC/Fusion Compiler, SpyGlass CDC/RDC checks, Low Power Architecture, Formality and others. - Be part, and, lead the Verification closure by interacting with the Verification teams - Drive the life-cycle of the Subsystems through various phases, from requirements to delivery. Key Qualifications for Design Engineers: - Hands-on/Lead experience on Subsystems/SOC Design, Architecture and Implementation. - Experience with Verilog/System Verilog coding and simulation tools . - Experience of implementation flows, namely: synthesis flow, lint, CDC, low power and others
