Construct SoC level test benches using verification components developed at the IP level. Test bench architecture for random/directed testing, stimulus generation, and checking to include custom and off the shelf VIP/UVCs.
Develop and execute SoC verification plans focused on IP block interoperability and SOC/System level. Develop and execute verification plans based on design specifications and collaboration with architects and designers.
Develop RAL test plan at SOC/IP level and its implementation. Verify SoC using advanced verification methodologies.
Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modeling (TLM), HW emulation/acceleration, and SW driven verification.
Work with design team to understand design intent and bring up verification plans and schedules.
You will think through design corner cases and be able to write relevant cover points.
Debug test cases and report verification result to achieve expected code/functional coverage goal. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.
Assist in emulation, FPGA, prototyping efforts.
Implement / maintain automated verification flows in languages such as Python, Perl/ Shell scripts.
Required Qualifications:
BSEE or MSEE, with experience in ASIC development and/or FPGA prototyping
7+ years of experience in RTL design using Verilog, SystemVerilog
Understanding of Digital Signal Processing theory, and mapping to design
Experience in WiFi Physical Layer, and/or other Physical layer like Cellular (WiMax, LTE, NR), Bluetooth, Zigbee, UWB, and/or other Physical layer (Ethernet) technologies
Ability to work independently, and proactively identify and resolve issues.
Experience with Incisive/Excellium/VCS, Verdi, Jasper/Spyglass or equivalent tools
Experience in partitioning, synthesis, placement, timing closure for FPGA and/or ASICs
Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs.
Enjoy debugging, and problem solving in a team environment.
Preferred Qualifications:
Master s degree in engineering (or equivalent) or Bachelor s degree in EE/EC/CS.
10+ years of experience in design verification - Proven experience in full chip verification from test plan development to tape-out sign-off. A good understanding of the complete verification life cycle (test plan, testbench through coverage closure)
Strong knowledge about multiple testbench architectures
Experience constructing chip-level System Verilog and UVM test bench environments, writing System Verilog Assertions (SVAs), with embedded software design and test.
Track record of successfully executing block or chip-level verification plans. HW/SW Co-Verification experience is a plus - Developing test benches, test cases/use-cases, APIs, their execution and debug on a FPGA/Emulation platform.
Expertise in developing RAL using UVM methodology and able to write all the UVM component like monitor, scoreboard, driver, agent etc from the scratch
Proficient working knowledge of AXI-lite/AXI-Stream/APB/AHB
Excellent debug skills, with experience debugging RTL in block and/or chip-level environments.
Proficient knowledge of VHDL, System Verilog, UVM, C and scripting languages like Python, Perl and Tcl.
Proficiency with Cadence design tools/environment and cadence UVCs is plus.
Excellent communication skills, energetic and self-motivated.
Work effectively with an off-site/off-shore design/DV team
