Hiringlabs Business Solutions
Location
Bangalore | India
Job description
Company Overview:
Hiringlabs Business Solutions is a leading staffing and recruiting company that specializes in providing top talent to organizations across various industries.
Role and Responsibilities:
The Memory Layout role involves the following responsibilities:
- Designing custom layout standard cell and memory layout as well as memory leafcell layout library from scratch including top level integration.
- Demonstrating good knowledge of different types of memory architectures and optimized layout design for improved performance.
- Applying sound knowledge and handson experience in FinFET technology layout design and addressing design rule check (DRC) limitations.
- Proficiency in physical verification flow and debug processes such as DRC LVS ERC and boundary conditions.
- Expertise in using Cadence Virtuoso layout editor and Calibre physical verification flow.
Candidate Qualifications:
The ideal candidate should possess the following qualifications:
- Relevant Bachelors or Masters degree in Electrical Engineering or a related field.
- Proven experience in custom layout standard cell and memory layout design.
- Demonstrated expertise in FinFET technology and layout design with a strong understanding of DRC limitations.
- Proficiency in utilizing Cadence Virtuoso layout editor and Calibre physical verification flow.
Required Skills:
The ideal candidate should have demonstrated skills in:
- Custom Layout
- Standard Cell
- Memory Layout Design
- FinFET Technology
- Physical Verification Flow
memory leafcell layout library design,calibre,drc,physical verification flow,std cell design,finfet technology,leafcell,custom layout,layout design,drc limitations,calibre physical verification flow,memory layout design,memory architectures,memory layout,lvs,cadence virtuoso layout editor
Job tags
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