BITSILICA
Location
Secunderabad | India
Job description
1.Skill: Senior/Lead IP/Soc Verification & ASIC RTL Design Engineers
2. Qualification : Bachelors / Masters in Electronics/VLSI/Embedded Systems
3. Experience : 5+ Years
4. Location : Hyderabad
Job Description:
5+ years of experience in IP/Soc design/verification, with a focus on complex IP blocks.
Strong understanding of High Speed Protocols and the associated verification challenges. Experience leading verification/desgn teams and driving verification projects to successful completion.
Lead the IP verification team, including defining the verification strategy, developing test plans, and executing tests.
Manage a team of verification engineers, providing technical guidance and mentoring as needed.
Work closely with the design team to ensure that the design meets the requirements and is testable.
Identify and drive improvements to the verification process to ensure the highest levels of quality and efficiency.
Job tags
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