ASIC Physical Design Lead
Location
Secunderabad | India
Job description
ASIC Physical Design Lead at VLSI/Semiconductor product MNC design center at Hyderabad
Job Summary:
We are looking for an ASIC Physical Design Lead with extensive experience in timing closure and full-chip physical design. The candidate should be adept at interacting with the packaging team and managing tasks such as pads log, bump placement, and RDL routing.
Key Responsibilities:
- Lead the physical design of complex ASIC projects from Netlist to GDSII.
- Perform timing closure tasks including synthesis, place and route, and static timing analysis.
- Oversee full-chip physical design processes, including floor planning, power grid design, clock tree synthesis, and signal integrity analysis.
- Collaborate with the packaging team to ensure seamless integration of the chip design with the package, including pads log management , bump placement , and RDL routing .
- Mentor junior engineers and guide them on physical design methodologies.
- Drive innovation and efficiency in physical design workflows.
Qualifications:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum of 10 years of experience in ASIC physical design.
- Expertise in industry-standard EDA tools for physical design and verification.
- Strong understanding of timing closure techniques and challenges.
- Experience with full-chip design and familiarity with multi-voltage and multi-clock domain designs.
- Excellent problem-solving and analytical skills.
- Strong communication and leadership abilities.
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