A dynamic startup is currently working on creating the most significant cluster of Synthetic Aperture Radar and AIS satellites for comprehensive ocean surveillance
They work in collaboration with NASA and the US Space Force and have received substantial investments from prominent backers in India
The ideal candidate will be a part of the Earth Observation Satellite Payload Development Team
Responsibilities:
As a member of the Earth Observation Satellite Payload Development Team, you will play a crucial role in designing and implementing FPGA-based digital solutions for the controller of SAR Payload
This project involves developing logic for High-Speed Data Converter interfaces, digital signal processing, and control logic, including bus interfaces and state machines
Develop RTL code to implement FPGA-based digital designs for the payload controller of SAR Payload.
Design the micro-architecture and code assigned modules in VHDL/Verilog.
Debug code using tools such as ChipScope and other debugging techniques.
Create test benches for verifying the design.
Perform FPGA debugging and hardware/software integration.
Qualifications:
B.Tech/MS/M.Tech. in computer or electrical engineering, or a related field
4+ years of experience in completing FPGA projects.
Hands-on coding experience in VHDL and/or Verilog coding.
Experience in targeting Xilinx and Microchip FPGAs.
Expertise in implementing designs with multiple clock domains.
A deep understanding of appropriate coding styles for FPGAs, with a focus on trade-offs for density and speed.
Experience in RTL implementation of DSP (Digital Signal Processing) algorithms will be highly valued.
Familiarity with interfaces like JESD, UART, Aurora, DRAM, SRAM, etc.
